Analysis of Total Ionizing Dose Effects on 0.13 µm Technology-Temperature-Compensated Voltage References

Both, Thiago Hanna; Colombo, Dalton; Dallasen, Ricardo Vanni; Wirth, Gilson Inácio

doi:10.5028/jatm.v5i3.227

ABSTRACT:

The purpose of this work is to briefly discuss the effects of the total ionizing dose (TID) on MOS devices in order to estimate the results of future irradiation tests on temperature-compensated voltage references that are implemented on a mixed-signal chip fabricated using IBM 0.13 µm technology. The analysis will mainly focus on the effects of the parametric variations on different voltage references. Monte-Carlo analyses were performed in order to determine the effects of threshold voltage shifts in each transistor on the output voltage.

KEYWORDS:
Ionizing dose; Radiation; TID; Voltage reference

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REFERENCES

Banba, H., Shiga, H., Umezawa, A., Miyaba, T., Tanzawa, T., Atsumi, S. and Sakui, K., 1999, “A CMOS bandgap reference circuit with sub-1-V operation”, IEEE Journal of Solid-State Circuits, Vol. 34, pp. 670-674.
Colombo, D., Fayomi, C., Nabki, F., Ferreira, L.F., Wirth, G. and Bampi, S., 2011, “A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References”, Journal of Integrated Circuits and Systems, Vol. 6.
Colombo, D., Werle, F., Wirth, G. and Bampi, S., 2012, “A CMOS 25.3 ppm/°C bandgap voltage reference using self-cascode composite transistor”, IEEE Third Latin American Symposium on Circuits and Systems (LASCAS), pp. 1-4.
Fleetwood, D.M. and Scofield, J.H., 1990, “Evidence that similar point defects cause 1/f noise and radiation-induced-hold trapping in metaloxide-semiconductor transistors”, Physical Review Letters, Vol. 64, pp. 579-582.
Fleetwood, D.M. Meisenheimer, T.L. and Scofield, J.H., 1994, “1/f noise and radiation effects in MOS devices”, IEEE Transactions on Electron Devices, Vol. 41, pp. 1953-1964.
Haugerud, B.M. Venkataraman, S., Sutton, A.K., Prakash, A.P.G., Cressler, J.D., Guofu Niu, Marshall, P.W. and Joseph, A.J., 2005, “The impact of substrate bias on proton damage in 130 nm CMOS technology”, IEEE Radiation Effects Data Workshop Proceedings, pp. 117-121.
Karnik, T. and Hazucha, P., 2004, “Characterization of soft errors caused by single event upsets in CMOS processes”, IEEE Transactions on Dependable and Secure Computing, Vol. 1, pp. 128-143.
Mavis, D.G. and Alexander, R., 1997, “Employing radiation hardness by design techniques with commercial integrated circuit processes”, Digital Avionics Systems Conference, 16th DASC., AIAA/IEEE, Vol. 1, pp. 15-22.
Meisenheimer, T.L. and Fleetwood, D.M., 1990, “Effect of Radiation-Induced Charge on 1/f Noise in MOS Devices”, IEEE Transactions on Nuclear Science, Vol. 37.
Oldham, T.R. and McLean, F.B., 2003, “Total Ionizing dose effects in MOS oxides and devices”, IEEE Transactions on Nuclear Science , Vol. 50, pp. 483-499.
Sexton, F.W., 2003, “Destructive single-event effects in semiconductor devices and ICs”, IEEE Transactions on Nuclear Science , Vol. 50, pp. 603-621.
Srour, J.R., 2003, “Review of displacement damage effects in silicon devices”, IEEE Transactions on Nuclear Science , Vol. 50, pp. 653-670.
Ueno, K., Hirose, T., Asai, T. and Amemiya, Y., 2009, “A 300 nW, 15 ppm/°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs”, IEEE Journal of Solid-State Circuits , Vol. 44, pp. 2047-2054.

Publication Dates

Publication in this collection
Jul-Sep 2013

History

Received
19 Jan 2013
Accepted
19 Apr 2013

This is an Open Access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

[1] Banba, H., Shiga, H., Umezawa, A., Miyaba, T., Tanzawa, T., Atsumi, S. and Sakui, K., 1999, “A CMOS bandgap reference circuit with sub-1-V operation”, IEEE Journal of Solid-State Circuits, Vol. 34, pp. 670-674.

[2] Colombo, D., Fayomi, C., Nabki, F., Ferreira, L.F., Wirth, G. and Bampi, S., 2011, “A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References”, Journal of Integrated Circuits and Systems, Vol. 6.

[3] Colombo, D., Werle, F., Wirth, G. and Bampi, S., 2012, “A CMOS 25.3 ppm/°C bandgap voltage reference using self-cascode composite transistor”, IEEE Third Latin American Symposium on Circuits and Systems (LASCAS), pp. 1-4.

[4] Fleetwood, D.M. and Scofield, J.H., 1990, “Evidence that similar point defects cause 1/f noise and radiation-induced-hold trapping in metaloxide-semiconductor transistors”, Physical Review Letters, Vol. 64, pp. 579-582.

[5] Fleetwood, D.M. Meisenheimer, T.L. and Scofield, J.H., 1994, “1/f noise and radiation effects in MOS devices”, IEEE Transactions on Electron Devices, Vol. 41, pp. 1953-1964.

[6] Haugerud, B.M. Venkataraman, S., Sutton, A.K., Prakash, A.P.G., Cressler, J.D., Guofu Niu, Marshall, P.W. and Joseph, A.J., 2005, “The impact of substrate bias on proton damage in 130 nm CMOS technology”, IEEE Radiation Effects Data Workshop Proceedings, pp. 117-121.

[7] Karnik, T. and Hazucha, P., 2004, “Characterization of soft errors caused by single event upsets in CMOS processes”, IEEE Transactions on Dependable and Secure Computing, Vol. 1, pp. 128-143.

[8] Mavis, D.G. and Alexander, R., 1997, “Employing radiation hardness by design techniques with commercial integrated circuit processes”, Digital Avionics Systems Conference, 16th DASC., AIAA/IEEE, Vol. 1, pp. 15-22.

[9] Meisenheimer, T.L. and Fleetwood, D.M., 1990, “Effect of Radiation-Induced Charge on 1/f Noise in MOS Devices”, IEEE Transactions on Nuclear Science, Vol. 37.

[10] Oldham, T.R. and McLean, F.B., 2003, “Total Ionizing dose effects in MOS oxides and devices”, IEEE Transactions on Nuclear Science , Vol. 50, pp. 483-499.

[11] Sexton, F.W., 2003, “Destructive single-event effects in semiconductor devices and ICs”, IEEE Transactions on Nuclear Science , Vol. 50, pp. 603-621.

[12] Srour, J.R., 2003, “Review of displacement damage effects in silicon devices”, IEEE Transactions on Nuclear Science , Vol. 50, pp. 653-670.

[13] Ueno, K., Hirose, T., Asai, T. and Amemiya, Y., 2009, “A 300 nW, 15 ppm/°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs”, IEEE Journal of Solid-State Circuits , Vol. 44, pp. 2047-2054.

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