An Asynchronous Interface with Robust Control for Globally-Asynchronous Locally-Synchronous Systems

Oliveira, Duarte Lopes de; Lussari, Eduardo; Sato, Sandro Shoiti; Faria, Lester de Abreu

doi:10.5028/jatm.v5i1.191

ABSTRACT:

Contemporary digital systems must necessarily be based on the "System-on-Chip" (SoC) concept. Especially in relation to the aerospace industry, these systems must overcome some additional engineering challenges concerning reliability, safety and low power. An interesting style for aerospace SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used for Very Large Scale Integration - Deep-Sub-Micron (VLSI_DSM) design. Currently, the major drawback in the design of a GALS system is the asynchronous interface (asynchronous wrapper - AW) when being implemented in VLSI_DSM. There is a typical AW design style based on asynchronous controllers that provides communication between modules (called ports), but the port controllers are generally subjected to essential hazard, what decreases the reliability and safety of the full system. Concerning to this main drawback, this paper proposes an AW with robust port controller that shows to be free of essential hazard, besides allowing full autonomy for the locally synchronous modules, creating fault tolerant systems as much as possible. It follows the Delay Insensitive (DI) model interacting with the environment in the Generalized Fundamental Mode (GFM) without the need to insert any delay elements. Additional delay elements, although proposed by some previous work found in literature, are not desirable in aerospace applications. The proposed interface allows working on Ib/Ob mode, showing the DI model is more robust than the QDI model and, therefore, it does not need to meet isochronic fork requirements nor timing analysis. Once an interface presenting similar properties was not found in literature, the proposed architecture proved to have great potential of implementation in practical VLSI_DSM designs, including the aerospace ones, once it overcomes the main engineering challenges of this kind of industry.

KEYWORDS:
Aerospace systems; Reliability; Low power; Asynchronous controllers; GALS

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REFERENCES

Amini, E., Najibi, M. and Pedram, H., 2006, "Globally asynchronous locally synchronous wrapper circuit based on clock gating", Emerging VLSI Technologies and Architectures, IEEE Computer Society Annual Symposium, Vol. 00, pp. 2-3.
Bertuccelli, L.F,, 2008, "Robust Decision-Making with Model Uncertainty in Aerospace Systems", Ph.D. thesis, MIT, September, 2008.
Bormann, D.S. and Cheung, P.Y.K., 1997, "Asynchronous Wrappers for Heterogeneous Systems," Proc. Int. Conf. Computer Design (ICCD), pp. 307-314.
Chapiro, D.M., 1984, "Globally-Asynchronous Locally-Synchronous Systems", PhD thesis, Stanford University, October, 1984.
Chu, T.A., 1987, "Synthesis of Self-Timed VLSI Circuits from Graph-Theory Specifications", Ph.D. thesis, Dept. of EECS, MIT, June, 1987.
Cortadella, J. et al., 1997, "Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers", IEICE Trans. Inf. Syst., Vol.E80-D, No. 3, pp. 315-325.
Davis, A.L. et al., 1979, "A data-driven machine architecture suitable for VLSI implementation", In C.L. Seitz, editor, Proc. of the Caltech Conf. on Very Large Scale Integration, pp. 179-194.
De Micheli, G. 2009, "An Outlook on Design Technologies for Future Integrated Systems", CAD of Integrated Circuits and Systems, Vol. 28, No.6, pp. 777-789.
Dobkin, R., Ginosar, R. and Sotiriou, C.P., 2006, "High Rate Data Synchronization in GALS SoCs", TVLSI, Vol. 14, No. 10, pp. 1063-1074.
Friedman, E.G., 2001, "Clock distribution networks in synchronous digital integrated circuits", Proc. IEEE, Vol. 89, No. 5, pp. 665-692.
Fuhrer, R.M. et al., 1999, "Minimalist: An environment for the Synthesis, verification and testability of burst-mode machines", Technical Report, Columbia University, TR-CUCS-020-99.
Ginosar, R., 2003, "Fourteen ways to fool your synchronizer", Proc. of ninth Int. Symp. On Async. Circuits and Systems, Vancouver, British Colombia, Canada, pp. 89-96.
Gurkaynak, F.K. et al., 2006, "GALS at ETH Zurich: Success or Failure?", Proc. 12^th IEEE Int. Symposium on Asynchronous Circuits and Systems, pp. 150-159.
Hardt, W. et. al., 2000, "Architecture Level Optimization for Asynchronous IPs", Proc. 13^th Annual IEEE Int. Conf. ASIC/SOC, pp.158-162.
Jain, A. et al., 2001, "A 1.2 GHz alpha microprocessor with 44.8 GB/s chip pin bandwidth", IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 240-241.
Jia, X., Vemuri, R., 2005, "Using GALS architecture to reduce the impact of long wire delay on FPGA performance", Proc. of the Asia and South Pacific Design automation Conf., pp. 1260-1263.
Krstic, M. et al., 2007, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook", IEEE Design & Test of Computers, Vol. 24, pp. 430-441.
Kumala, A. et al., 2006, "Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA", Int. Conf. on Field Programmable Logic and Application, pp. 1-6.
Martin, A.J. and Nystrom, M., "Asynchronous Techniques for System-on-Chip Design", Proc. of the IEEE, Vol.94, No. 6, pp. 1089-1120.
Miller, S.P. et al., 2005, "A Methodology for the Design and Verification of Globally Asynchronous/Locally Synchronous Architectures", NASA/CR-2005-213912, pp. 1-35.
Muller-Glaser, K.D. et. al., 2004, "Multiparadigm Modeling in Embedded Systems Design", IEEE Trans. on Control Systems Technology, Vol. 12, No. 2.
Mullins, R. and Moore, S., 2007, "Demystifying Data-Driven and Pausible Clocking Schemes", Proc. of ASYNC'07, pp. 175-185.
Muttersbach, J., Villiger, T. and Fichtner,W., 2000, "Practical Design of Globally-asynchronous Locally-synchronous System", Proc. IEEE 6^th Int. Symposium Advanced Research in Asynchronous Circuits and Systems, pp. 52-59.
Muttersbach, J. 2001, "Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems", Ph.D. Thesis, ETH, Zurich, 2001.
Myers, C.J. 2000, "Asynchronous Circuit Design", Wiley & Sons, Inc., 2004, 2nd edition.
Nowick, S.M, 1993, "Automatic Synthesis of Burst-Mode Asynchronous Controllers", PhD thesis, Stanford University, 1993.
Oliveira, D.L. et al., 2008, "Burst-Mode Asynchronous Controllers on FPGA", Int. Journal of Reconfigurable Computing, Vol. 2008, pp. 1-10.
Oliveira, D.L. et al., 2011, "Synthesis of Robust Conrollers for GALS_FPGA from Multi-Burst Graph Specification", Proc. IEEE VII Southern Conference on Programmable Logic (SPL), pp. 123-129.
Pontes, J. et al., 2007, "SCAFFI: an Intrachip FPGA asynchronous interface based on hard macros", 25^th Int. Conf. on Computer Design, pp. 541-546.
Reddy Ravi, A., 2001, "Globally-Asynchronous, Locally-Synchronous Wrapper Configurations for Ponint-to-Point and Multi-Point Data Comunication", Masters of Science, University of Central Florida, 2001.
Sjogren, A.E. and Myers, C.J., 2000, "Interfacing Synchronous and Asynchronous Modules within a High-Speed Pipeline", IEEE Transactions on VLSI Systems, Vol. 8, No. 5, pp. 573-583.
Sues, R.H. et al., 2005, "Reliability-Based MDO for Aerospace Systems", AIAA-2001-1521, pp. 1-8.
Techan, P., Greenstreet, M. and Lemieux,G., 2007, "A Survey and Taxonomy of GALS Design Styles", IEEE Design & Test of Computers, Vol. 24, pp. 418-428.
Unger, S.H. 1969, "Asynchronous Sequential Switching Circuits", John Wiley & Sons Inc.
Yuan, L. et al., 2008, "Research on the Problems of Satellite Borne FPGA Based Finite State Machine", 2^nd Int. Symposium on Systems and Control in Aerospace and Astronautics (ISSCAA), pp. 1-4.
Yun, K.Y. and Dill, D.L., 1999, "Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-Free Implementation) and Part II (Automatic Synthesis)", IEEE Trans. on CAD of Integrated Circuit and Systems, Vol. 18:2, pp. 101-132.
Yun, K.Y. and Donohue, R.P., 1999, "Pausible clocking-based heterogeneous systems", IEEE Transactions on VLSI Systems, Vol. 7, No. 4, pp. 482-488.

Publication Dates

Publication in this collection
Jan-Mar 2013

History

Received
14 Nov 2012
Accepted
18 Jan 2013

This is an Open Access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

[1] Amini, E., Najibi, M. and Pedram, H., 2006, "Globally asynchronous locally synchronous wrapper circuit based on clock gating", Emerging VLSI Technologies and Architectures, IEEE Computer Society Annual Symposium, Vol. 00, pp. 2-3.

[2] Bertuccelli, L.F,, 2008, "Robust Decision-Making with Model Uncertainty in Aerospace Systems", Ph.D. thesis, MIT, September, 2008.

[3] Bormann, D.S. and Cheung, P.Y.K., 1997, "Asynchronous Wrappers for Heterogeneous Systems," Proc. Int. Conf. Computer Design (ICCD), pp. 307-314.

[4] Chapiro, D.M., 1984, "Globally-Asynchronous Locally-Synchronous Systems", PhD thesis, Stanford University, October, 1984.

[5] Chu, T.A., 1987, "Synthesis of Self-Timed VLSI Circuits from Graph-Theory Specifications", Ph.D. thesis, Dept. of EECS, MIT, June, 1987.

[6] Cortadella, J. et al., 1997, "Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers", IEICE Trans. Inf. Syst., Vol.E80-D, No. 3, pp. 315-325.

[7] Davis, A.L. et al., 1979, "A data-driven machine architecture suitable for VLSI implementation", In C.L. Seitz, editor, Proc. of the Caltech Conf. on Very Large Scale Integration, pp. 179-194.

[8] De Micheli, G. 2009, "An Outlook on Design Technologies for Future Integrated Systems", CAD of Integrated Circuits and Systems, Vol. 28, No.6, pp. 777-789.

[9] Dobkin, R., Ginosar, R. and Sotiriou, C.P., 2006, "High Rate Data Synchronization in GALS SoCs", TVLSI, Vol. 14, No. 10, pp. 1063-1074.

[10] Friedman, E.G., 2001, "Clock distribution networks in synchronous digital integrated circuits", Proc. IEEE, Vol. 89, No. 5, pp. 665-692.

[11] Fuhrer, R.M. et al., 1999, "Minimalist: An environment for the Synthesis, verification and testability of burst-mode machines", Technical Report, Columbia University, TR-CUCS-020-99.

[12] Ginosar, R., 2003, "Fourteen ways to fool your synchronizer", Proc. of ninth Int. Symp. On Async. Circuits and Systems, Vancouver, British Colombia, Canada, pp. 89-96.

[13] Gurkaynak, F.K. et al., 2006, "GALS at ETH Zurich: Success or Failure?", Proc. 12^th IEEE Int. Symposium on Asynchronous Circuits and Systems, pp. 150-159.

[14] Hardt, W. et. al., 2000, "Architecture Level Optimization for Asynchronous IPs", Proc. 13^th Annual IEEE Int. Conf. ASIC/SOC, pp.158-162.

[15] Jain, A. et al., 2001, "A 1.2 GHz alpha microprocessor with 44.8 GB/s chip pin bandwidth", IEEE Int. Solid-State Circuits Conf. Tech. Dig., pp. 240-241.

[16] Jia, X., Vemuri, R., 2005, "Using GALS architecture to reduce the impact of long wire delay on FPGA performance", Proc. of the Asia and South Pacific Design automation Conf., pp. 1260-1263.

[17] Krstic, M. et al., 2007, "Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook", IEEE Design & Test of Computers, Vol. 24, pp. 430-441.

[18] Kumala, A. et al., 2006, "Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA", Int. Conf. on Field Programmable Logic and Application, pp. 1-6.

[19] Martin, A.J. and Nystrom, M., "Asynchronous Techniques for System-on-Chip Design", Proc. of the IEEE, Vol.94, No. 6, pp. 1089-1120.

[20] Miller, S.P. et al., 2005, "A Methodology for the Design and Verification of Globally Asynchronous/Locally Synchronous Architectures", NASA/CR-2005-213912, pp. 1-35.

[21] Muller-Glaser, K.D. et. al., 2004, "Multiparadigm Modeling in Embedded Systems Design", IEEE Trans. on Control Systems Technology, Vol. 12, No. 2.

[22] Mullins, R. and Moore, S., 2007, "Demystifying Data-Driven and Pausible Clocking Schemes", Proc. of ASYNC'07, pp. 175-185.

[23] Muttersbach, J., Villiger, T. and Fichtner,W., 2000, "Practical Design of Globally-asynchronous Locally-synchronous System", Proc. IEEE 6^th Int. Symposium Advanced Research in Asynchronous Circuits and Systems, pp. 52-59.

[24] Muttersbach, J. 2001, "Globally-Asynchronous Locally-Synchronous Architectures for VLSI Systems", Ph.D. Thesis, ETH, Zurich, 2001.

[25] Myers, C.J. 2000, "Asynchronous Circuit Design", Wiley & Sons, Inc., 2004, 2nd edition.

[26] Nowick, S.M, 1993, "Automatic Synthesis of Burst-Mode Asynchronous Controllers", PhD thesis, Stanford University, 1993.

[27] Oliveira, D.L. et al., 2008, "Burst-Mode Asynchronous Controllers on FPGA", Int. Journal of Reconfigurable Computing, Vol. 2008, pp. 1-10.

[28] Oliveira, D.L. et al., 2011, "Synthesis of Robust Conrollers for GALS_FPGA from Multi-Burst Graph Specification", Proc. IEEE VII Southern Conference on Programmable Logic (SPL), pp. 123-129.

[29] Pontes, J. et al., 2007, "SCAFFI: an Intrachip FPGA asynchronous interface based on hard macros", 25^th Int. Conf. on Computer Design, pp. 541-546.

[30] Reddy Ravi, A., 2001, "Globally-Asynchronous, Locally-Synchronous Wrapper Configurations for Ponint-to-Point and Multi-Point Data Comunication", Masters of Science, University of Central Florida, 2001.

[31] Sjogren, A.E. and Myers, C.J., 2000, "Interfacing Synchronous and Asynchronous Modules within a High-Speed Pipeline", IEEE Transactions on VLSI Systems, Vol. 8, No. 5, pp. 573-583.

[32] Sues, R.H. et al., 2005, "Reliability-Based MDO for Aerospace Systems", AIAA-2001-1521, pp. 1-8.

[33] Techan, P., Greenstreet, M. and Lemieux,G., 2007, "A Survey and Taxonomy of GALS Design Styles", IEEE Design & Test of Computers, Vol. 24, pp. 418-428.

[34] Unger, S.H. 1969, "Asynchronous Sequential Switching Circuits", John Wiley & Sons Inc.

[35] Yuan, L. et al., 2008, "Research on the Problems of Satellite Borne FPGA Based Finite State Machine", 2^nd Int. Symposium on Systems and Control in Aerospace and Astronautics (ISSCAA), pp. 1-4.

[36] Yun, K.Y. and Dill, D.L., 1999, "Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-Free Implementation) and Part II (Automatic Synthesis)", IEEE Trans. on CAD of Integrated Circuit and Systems, Vol. 18:2, pp. 101-132.

[37] Yun, K.Y. and Donohue, R.P., 1999, "Pausible clocking-based heterogeneous systems", IEEE Transactions on VLSI Systems, Vol. 7, No. 4, pp. 482-488.

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